liminfoCadence Virtuoso Reference
Free reference guide: Cadence Virtuoso Reference
About Cadence Virtuoso Reference
The Cadence EDA Reference is a comprehensive cheat sheet for the Cadence Design Systems tool suite, organized into six categories: Virtuoso (analog/mixed-signal design), DRC/LVS verification, Innovus (digital place-and-route), Genus (RTL synthesis), Xcelium (simulation), and SKILL scripting. Each entry provides the command or concept name, a description, and copy-ready code examples.
This reference covers the complete IC design flow from schematic capture through physical verification. The Virtuoso section includes library management with cds.lib, schematic/layout editor key bindings, ADE simulation setup with Spectre, and QRC parasitic extraction. The DRC/LVS section details Calibre command-line execution, SVRF rule file syntax, and PEX output formats (DSPF, SPEF, Calibre View).
The digital design sections cover the Genus synthesis flow (syn_generic, syn_map, syn_opt) with library setup and SDC constraint reading, the Innovus P&R flow from floorplan through CTS and routing to final GDS/SPEF export, Xcelium simulation with xrun including UVM, coverage, and gate-level SDF back-annotation, and SKILL programming for layout automation and custom Virtuoso menu integration.
Key Features
- Virtuoso library management (cds.lib), schematic editor key bindings (i/w/p/q), and layout editor shortcuts (r/p/k/Tab) with SKILL examples
- ADE-L simulation setup for DC, AC, and transient analysis with Spectre, including parametric sweeps and result plotting
- Calibre DRC command-line syntax, SVRF rule file layer mapping, and width/spacing/enclosure rule examples
- Calibre LVS execution flow, result status codes (CORRECT/Short/Open/Property), and SKILL-based LVS invocation
- Innovus P&R flow from init_design and floorPlan through place_design, CTS (ccopt_design), routing, and post-route optimization
- Genus synthesis stages (syn_generic/syn_map/syn_opt) with library setup, SDC reading, and Innovus handoff via write_design
- Xcelium xrun single-command flow for SystemVerilog+UVM, SHM waveform dump, coverage collection, and gate-level simulation with SDF
- SKILL programming fundamentals, cellview/instance traversal, layout rectangle/path/via creation, and custom menu registration
Frequently Asked Questions
What Cadence tools does this reference cover?
This reference covers the six core Cadence EDA tools: Virtuoso for analog schematic/layout/simulation (including ADE-L with Spectre), Calibre for DRC/LVS/PEX physical verification, Innovus for digital place-and-route, Genus for RTL-to-gate synthesis, Xcelium for digital simulation (Verilog/SystemVerilog/VHDL/UVM), and the SKILL programming language for Virtuoso automation and customization.
How do I set up a Virtuoso library with cds.lib?
Create a cds.lib file with DEFINE statements mapping library names to paths. For example: "DEFINE myLib ./myLib" for your design library, "DEFINE analogLib $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/analogLib" for the standard analog library, and "DEFINE basic $CDS_INST_DIR/tools/dfII/etc/cdslib/basic" for basic cells. Each library contains cells with views like schematic, symbol, layout, and extracted.
What are the essential Virtuoso schematic editor key bindings?
The most important key bindings are: i (Instance placement), w (Wire), p (Pin), l (Label), c (Copy), m (Move), u (Undo), q (Property edit), f (Fit/zoom all), e (Descend into subcell), and Ctrl+e (Return to parent). In the layout editor, additional keys include r (Rectangle), k (Ruler), Shift+k (Clear rulers), s (Stretch), and Tab (Change layer).
How do I run Calibre DRC from the command line?
Execute "calibre -drc -hier top.svrf top.gds" where top.svrf is your SVRF rule file containing layer maps and DRC rules, and top.gds is the layout. The SVRF file defines layer mappings (e.g., "1 DATATYPE 0 1001" for NWELL) and rules using geometric operations like INT (internal), EXT (external), and ENCLOSURE. View results in Calibre RVE or highlight errors directly in Virtuoso.
What is the Innovus digital place-and-route flow?
The standard Innovus flow is: 1) init_design with netlist, LEF, and MMMC view files, 2) floorPlan to define die area and core margins, 3) addRing/addStripe for power distribution, 4) place_design for cell placement, 5) CTS with ccopt_design, 6) optDesign for pre/post-CTS timing optimization, 7) routeDesign for global and detail routing, 8) post-route optimization with hold fixing, and 9) streamOut for GDS export.
How does Genus synthesis work in stages?
Genus synthesis proceeds through three stages: syn_generic performs technology-independent optimization on the RTL, syn_map performs technology mapping to the target standard cell library, and syn_opt performs final optimization. Each stage supports effort levels (set_db syn_generic_effort high). After synthesis, use write_design -innovus to generate files directly readable by Innovus for place-and-route.
How do I run a UVM testbench with Xcelium?
Use the xrun single-command flow: "xrun -sv top.sv tb_top.sv -uvm +UVM_TESTNAME=base_test -access +rwc -timescale 1ns/1ps". The -uvm flag enables UVM library support, +UVM_TESTNAME selects the test, -access +rwc enables read/write/connectivity access for debugging, and -timescale sets the simulation time resolution. For waveform capture, add "-input probe.tcl" with SHM database probing commands.
What can I automate with SKILL scripting in Virtuoso?
SKILL can automate virtually any Virtuoso operation: opening/closing cellviews with dbOpenCellViewByType, traversing instances and nets via cv~>instances and cv~>nets, creating layout geometry (dbCreateRect, dbCreatePath, dbCreateVia), reading/writing instance properties with dbGet/dbSet, adding custom menus with hiCreateMenuItem/hiInsertBannerMenu, and building complete parameterized cell (pcell) generators.