I2C Reference

I2C (Inter-Integrated Circuit) is a synchronous, multi-master, multi-slave, two-wire serial communication protocol. It uses SDA (Serial Data) and SCL (Serial Clock) lines, both requiring pull-up resistors to VDD. The master generates the clock and initiates all transfers. Communication begins with a START condition (SDA falls while SCL is HIGH), proceeds with address and data bytes each acknowledged by the receiver, and ends with a STOP condition (SDA rises while SCL is HIGH).

The optimal pull-up resistor depends on bus speed and bus capacitance. For Standard Mode (100kHz) at 3.3V, 10kΩ is typical. For Fast Mode (400kHz) at 3.3V, 4.7kΩ is recommended. For Fast Mode Plus (1MHz), 2.2kΩ or lower may be needed. The minimum resistor is (VDD - VOL) / IOL — at 3.3V with 3mA sink current this gives about 967Ω. Too high a value slows rise times and causes communication errors at higher speeds.

A single byte read sends START, the device address + W bit, the register address, then a Repeated START followed by the device address + R bit, reads one byte, sends NACK, and STOP. A burst read is identical but instead of NACK after the first byte, the master sends ACK to request more bytes — the device auto-increments the register pointer. This is essential for reading multi-byte values like accelerometer XYZ data (6 bytes) in a single transaction.

Clock Stretching allows a slave device to hold the SCL line LOW after the master releases it, effectively pausing the communication until the slave is ready to send or receive the next byte. This is used when the slave needs extra time to process data (e.g., performing an ADC conversion). Not all I2C masters support Clock Stretching — check the master's datasheet. If it is not supported, the slave must be fast enough to respond within the master's timing window.

Install i2c-tools and run sudo i2cdetect -y 1 (replace 1 with your I2C bus number). The command scans the bus and prints a grid showing addresses where devices respond with ACK. Addresses appear as hex values; dashes (--) indicate no device. To read a register: sudo i2cget -y 1 0x48 0x00 w. To write a register: sudo i2cset -y 1 0x48 0x01 0x60. To dump all registers: sudo i2cdump -y 1 0x48.

When two masters attempt to start a transfer simultaneously, arbitration resolves the conflict bit by bit on the SDA line. Each master monitors SDA while transmitting — if a master drives SDA HIGH but reads it as LOW, another master is driving it LOW and wins the arbitration. The losing master immediately stops transmitting and waits. This works because I2C SDA is open-drain: any master can pull it LOW, but none can drive it HIGH against another pulling LOW.

A bus lockup occurs when a slave is mid-transfer during a power cycle and holds SDA LOW indefinitely. Recovery procedure: set SCL as output and toggle it HIGH/LOW 9 times — this clocks out the remaining bits in the slave's shift register. Then generate a STOP condition (drive SDA LOW, then SCL HIGH, then SDA HIGH). If the slave's firmware supports software reset, send a General Call Reset (0x00, 0x06) after recovery.

Serial EEPROMs (like the AT24C256) are internally organized into pages of fixed size (e.g., 64 bytes for AT24C256). A write that crosses a page boundary wraps around to the beginning of the same page rather than advancing to the next page, corrupting data. When writing more than one page, you must split the write at page boundaries and insert the required write cycle delay (typically 5ms for 24-series EEPROMs) between each page write.