liminfoPCB Design Rules
Free reference guide: PCB Design Rules
About PCB Design Rules
The PCB Design Rules Reference is a comprehensive, searchable quick-reference covering essential printed circuit board design guidelines and IPC standards that every PCB designer and electrical engineer needs. It covers trace width versus current capacity tables for both external and internal layers per IPC-2221 with the current calculation formula (I = k times dT^0.44 times A^0.725), copper weight correction factors for 0.5oz through 3oz, minimum trace/space clearance rules based on voltage ratings, and creepage distance requirements for high-voltage designs.
The reference provides detailed via and pad design rules including through-hole, blind, buried, and microvia sizing with recommended aspect ratios, thermal relief pad patterns for ground and power connections, pad-to-hole ratios, via current capacity, and via-in-pad design considerations. Impedance and signal integrity coverage includes single-ended microstrip and stripline formulas with typical target impedances (50 ohm SE, 90/100 ohm differential), differential pair routing rules, length matching tolerances for high-speed interfaces (DDR, USB, PCIe), and return path continuity guidelines for reference plane transitions.
For power delivery and manufacturing, the reference covers power plane design rules (decoupling capacitor placement, copper pour connections, split plane management), thermal management (thermal via arrays, copper area calculations for heat dissipation), and comprehensive DFM (Design for Manufacturability) rules including minimum annular ring, solder mask dam, silkscreen clearance, panelization requirements, drill-to-copper clearance, acid trap avoidance, and standard fabrication capabilities across PCB manufacturers.
Key Features
- IPC-2221 trace width vs current tables for external (k=0.048) and internal (k=0.024) layers with copper weight corrections
- Voltage-based clearance and creepage distance rules for PCB spacing at various voltage levels
- Via sizing guide: through-hole, blind, buried, and microvia with aspect ratios, current capacity, and via-in-pad rules
- Impedance formulas for single-ended microstrip/stripline (50 ohm) and differential pairs (90/100 ohm) with stackup guidance
- High-speed signal integrity: length matching tolerances, return path continuity, and differential pair routing rules
- Power plane design: decoupling strategy, copper pour, split plane management, and thermal via array sizing
- Complete DFM rule set: minimum annular ring, solder mask dam, silkscreen clearance, and drill specifications
- Manufacturing capability reference: standard PCB fab tolerances, panelization rules, and acid trap avoidance guidelines
Frequently Asked Questions
How do I calculate trace width for a given current?
Use the IPC-2221 formula: I = k times dT^0.44 times A^0.725, where k = 0.048 for external layers and 0.024 for internal layers, dT is the temperature rise in degrees C, and A is the trace cross-section area in mil squared (width times thickness, with 1oz copper = 1.378 mil). For example, at 10 degrees C rise with 1oz copper on external layers: 1A needs 20 mil width, 3A needs 80 mil, and 5A needs 150 mil. Internal layers require roughly double the width due to poorer heat dissipation.
What clearance is needed between traces at different voltages?
The reference provides IPC-based clearance rules scaled by voltage. For typical internal layers, clearances range from 4 mil at low voltage up to hundreds of mils for high-voltage applications. Creepage distances on external surfaces must also be considered, especially for safety certifications. The specific values depend on the pollution degree, material group, and whether the spacing is internal or external.
What are the recommended via sizes and aspect ratios?
Standard through-hole vias typically use drill diameters of 8-12 mil with aspect ratios (board thickness to drill diameter) of 8:1 to 10:1 for reliable plating. Microvias are typically 3-5 mil diameter with a maximum aspect ratio of 1:1. The reference includes blind and buried via rules, via current capacity guidelines, thermal relief patterns, and via-in-pad design considerations for BGA breakout.
How do I achieve 50-ohm impedance on a PCB?
The reference provides microstrip and stripline impedance formulas. For single-ended 50 ohm microstrip, trace width depends on dielectric thickness, dielectric constant (typically Er = 4.2-4.5 for FR-4), and copper thickness. Common stackups target 50 ohm single-ended and 100 ohm differential. The tool includes guidance on stackup planning, dielectric selection, and impedance calculator inputs for your PCB fabricator.
What length matching tolerances are needed for high-speed signals?
Length matching requirements vary by interface: DDR3/DDR4 data lanes typically need matching within 5-25 mil within a byte group, USB differential pairs within 5 mil, PCIe within 5 mil per pair, and HDMI within 5 mil. The reference covers both intra-pair (P to N) and inter-pair (lane to lane) matching rules, as well as via delay compensation.
How should I design power planes and decoupling?
The reference covers decoupling capacitor placement (as close to power pins as possible, with via connections to planes), copper pour connectivity rules, split plane management (avoiding signal routes crossing splits), and thermal relief patterns. It includes guidelines for power plane current density, via connections to planes, and stitching capacitor placement at plane splits.
What DFM rules should I follow for reliable PCB manufacturing?
Key DFM rules include: minimum annular ring (typically 3-5 mil), solder mask dam between pads (typically 3-4 mil minimum), silkscreen clearance from pads (4 mil), minimum drill size (8 mil for standard, 4 mil for HDI), drill-to-copper clearance (8 mil), and acid trap avoidance (no acute angles in copper). The reference also covers panelization breakaway tab placement and board edge clearance requirements.
How do I design thermal vias for heat dissipation?
The reference covers thermal via array design for exposed pad components: typical via diameter of 10-12 mil, spacing of 40-50 mil in a grid pattern, filled and capped vias to prevent solder wicking, and copper area calculations for thermal pads. It also covers thermal relief patterns for through-hole components on power/ground planes to balance thermal dissipation with solderability.