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Synopsys Reference

Free reference guide: Synopsys Reference

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About Synopsys Reference

The Synopsys EDA Reference is a practical command reference covering the five core tools in the Synopsys digital design flow: Design Compiler (logic synthesis), PrimeTime (static timing analysis), VCS (simulation), IC Compiler II (place and route), and common Tcl scripting patterns. Each entry includes the actual Tcl command syntax with realistic usage examples that reflect production ASIC/FPGA design workflows.

The Design Compiler section covers the complete RTL-to-gate synthesis flow from read_file and library setup through clock constraints (create_clock, set_clock_uncertainty), I/O timing constraints (set_input_delay, set_output_delay, set_driving_cell), advanced synthesis (compile_ultra with retiming, gate clocking, area optimization), reporting (timing, area, power, QoR), and netlist/SDC/SDF export. The PrimeTime section addresses STA setup, multi-corner analysis, CPPR, POCV/AOCV variation analysis, and ECO timing closure.

The VCS simulation section demonstrates compilation options for SystemVerilog and UVM testbenches, waveform dumping (VCD/FSDB), code coverage collection, and Verdi debugger integration. The ICC2 section covers NDM library creation, floorplanning, placement optimization (place_opt), clock tree synthesis (clock_opt), auto-routing, DRC/LVS checks, and GDSII export. Common Tcl patterns include get_cells/get_nets/get_pins queries, cell optimization controls (set_dont_touch, size_cell), and SAIF-based power analysis.

Key Features

  • Design Compiler synthesis flow from RTL read through compile_ultra to gate-level netlist export
  • Clock constraint definition including generated clocks, uncertainty, transition, and latency settings
  • PrimeTime STA with setup/hold analysis, CPPR, crosstalk, and POCV/AOCV on-chip variation support
  • VCS compilation and simulation with SystemVerilog, UVM, coverage, and Verdi FSDB waveform integration
  • ICC2 place-and-route flow covering NDM setup, placement, CTS, routing, filler insertion, and GDS export
  • ECO timing closure workflow with size_cell, insert_buffer, swap_cell commands and timing update
  • SAIF-based switching activity power analysis with PrimeTime and Design Compiler power optimization
  • Common Tcl object query patterns with get_cells, get_nets, get_pins filtering and foreach iteration

Frequently Asked Questions

What Synopsys tools are covered in this reference?

This reference covers five core Synopsys tools: Design Compiler (DC) for logic synthesis, PrimeTime (PT) for static timing analysis, VCS for RTL and gate-level simulation, IC Compiler II (ICC2) for physical design (place and route), and common Tcl scripting commands shared across these tools. It also covers Verdi waveform debugging integration with VCS.

How do I set up clock constraints in Design Compiler?

Use create_clock to define the primary clock with period and source port. Add set_clock_uncertainty for jitter/skew margin, set_clock_transition for slew, and set_clock_latency for source and network latency. For divided clocks, use create_generated_clock with -source and -divide_by options pointing to the divider register output pin.

What is the difference between compile and compile_ultra?

compile_ultra uses advanced optimization algorithms including automatic ungrouping, datapath optimization, and DesignWare implementation selection for better timing and area results. Key options include -retime for pipeline retiming, -gate_clock for clock gating insertion, -incremental for post-synthesis re-optimization, and -area_high_effort_script for area-focused optimization.

How do I run PrimeTime static timing analysis?

Read the gate-level netlist with read_verilog, link the design, read parasitics (SPEF format), and apply SDC constraints with read_sdc. Use report_timing with -delay_type max for setup checks and -delay_type min for hold checks. For advanced analysis, enable POCV/AOCV for on-chip variation modeling and CPPR for clock path pessimism removal.

What is POCV/AOCV in PrimeTime?

POCV (Parametric OCV) and AOCV (Advanced OCV) are methods for modeling on-chip process variation more accurately than flat OCV derating. AOCV uses depth-based and distance-based derating tables, while POCV uses statistical coefficients per cell/arc. Both reduce unnecessary pessimism compared to flat derate factors (e.g., 5% early/late), enabling more realistic timing analysis and fewer false violations.

How do I compile and run a UVM testbench with VCS?

Compile with vcs -full64 -sverilog, include the UVM source with +incdir+$UVM_HOME/src and $UVM_HOME/src/uvm_pkg.sv, add -ntb_opts uvm, and specify the test with +UVM_TESTNAME=test_name. For waveform debugging, add -kdb -debug_access+all and link the Verdi PLI libraries to enable FSDB dump.

What is the ICC2 place-and-route flow?

The ICC2 flow starts with NDM library creation (create_lib), netlist reading and linking, floorplan/DEF loading, and UPF power intent. Then run place_opt for placement, clock_opt for CTS, route_auto for global/detail routing, and route_opt for post-route optimization. Finally, insert filler cells, run DRC/LVS checks, and export GDSII, final netlist, and SPEF parasitics.

How do I perform power analysis with Synopsys tools?

In VCS simulation, use $toggle_start/$toggle_stop and $toggle_report to generate a SAIF (Switching Activity Interchange Format) file. In PrimeTime, read the SAIF with read_saif, run update_power, and use report_power for hierarchical power breakdown. In Design Compiler, set_max_dynamic_power and compile_ultra -gate_clock -power optimize power during synthesis.