Verilog Reference

Q: How do I prevent unintended latches in combinational logic?

Three rules prevent latches: (1) assign default values at the beginning of combinational always @(*) blocks, (2) always include a default case in case statements, and (3) ensure every output is assigned in every possible path through the logic. The reference includes examples of each prevention technique.

Q: How do I write a testbench in Verilog?

A testbench module has no ports. Declare reg signals for DUT inputs and wire signals for DUT outputs. Generate a clock with "always #5 clk = ~clk". Use initial blocks for reset sequences and stimulus. Include $dumpfile/$dumpvars for waveform output. The reference provides a complete testbench template with self-checking assertions.

Q: What are CDC techniques for clock domain crossing?

For single-bit signals, use a 2-FF synchronizer: two flip-flops in the destination clock domain to reduce metastability probability. For multi-bit signals, use Gray code encoding or an asynchronous FIFO. For pulse transfer, use a toggle-based handshake synchronizer. The reference includes complete code examples for each technique.

Q: What synthesis attributes does this reference include?

The reference covers Xilinx attributes (dont_touch, mark_debug, ram_style for BRAM/LUTRAM selection, fsm_encoding for one-hot/binary), Intel/Altera attributes (syn_encoding), and general synthesis pragmas (translate_off/on for simulation-only code, full_case/parallel_case for case optimization).

Free reference guide: Verilog Reference

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About Verilog Reference

The Verilog Reference is a comprehensive, searchable guide to Verilog HDL covering basic syntax (module declarations, wire/reg types, number literals, parameters, assign statements, operators), sequential logic patterns (always @(posedge clk) flip-flops, combinational always @(*) blocks, if-else/case statements, counters, FSMs, shift registers), structural design (module instantiation, generate constructs, memory inference), testbench techniques, and synthesis directives.

This reference includes 20 detailed entries organized into five categories with complete, copy-ready code examples. Every entry demonstrates real RTL patterns: D flip-flops with synchronous and asynchronous reset, priority encoders using casex, 3-block FSM state machines, SIPO/PISO shift registers, synchronous single/dual-port RAM inference, parameterized module instantiation with generate loops, CDC 2-FF synchronizers, and Xilinx/Altera synthesis attributes.

Whether you are designing FPGA logic for Xilinx Vivado or Intel Quartus, writing RTL for ASIC synthesis, building testbenches with self-checking assertions, or studying digital design fundamentals, this reference provides instant access to every Verilog construct with practical examples. All content runs entirely in your browser with no server processing required.

Key Features

Complete module declaration syntax with port definitions, wire/reg types, number literals (binary, hex, decimal), and parameter/localparam constants
Sequential logic patterns including D flip-flops (sync/async reset, enable), always @(posedge clk) blocks with non-blocking assignments, and counter designs
Combinational logic reference with always @(*) blocks, multiplexers, priority encoders, decoders, and latch prevention rules
FSM design template with standard 3-block pattern (state register, next-state logic, output logic) using localparam state encoding
Structural design examples covering named port instantiation, parameter overrides, generate for/if/case constructs, and single/dual-port RAM inference
Testbench templates with clock generation, DUT instantiation, stimulus timing, system tasks ($display, $monitor, $readmemh), and self-checking patterns
Synthesis coding rules including latch prevention, blocking vs non-blocking assignment guidelines, CDC 2-FF synchronizers, and FPGA vendor attributes
Full operator reference covering arithmetic, logical, bitwise, reduction, shift, and comparison operators with precedence information

Frequently Asked Questions

What Verilog topics does this reference cover?

This reference covers five categories: Basic Syntax (module, wire/reg, literals, parameters, assign, operators), Sequential Logic (flip-flops, always blocks, if-else/case, counters, FSMs, shift registers), Structural Design (instantiation, generate, memory), Testbench (structure, initial blocks, system tasks, assertions), and Synthesis Directives (coding rules, CDC, attributes, timing).

When should I use wire vs reg in Verilog?

Use wire for continuous assignments (assign statements) and module output connections. Use reg for values assigned inside always blocks. Note that reg does not always infer a hardware register; in combinational always @(*) blocks, reg variables synthesize to combinational logic. The key rule is: wire for assign, reg for always.

How do I write a proper FSM in Verilog?

Use the standard 3-block FSM pattern: Block 1 is a synchronous always block for the state register (always @(posedge clk)). Block 2 is a combinational always @(*) block for next-state logic with a case statement. Block 3 is a combinational always block for output logic. Define states using localparam. Always include a default assignment for next_state to prevent latches.

What is the difference between blocking and non-blocking assignments?

Use non-blocking assignments (<=) in sequential always @(posedge clk) blocks to correctly model flip-flop behavior. Use blocking assignments (=) in combinational always @(*) blocks. Mixing them in the same block can cause simulation mismatches with synthesis. This is one of the most important Verilog coding rules.

How do I prevent unintended latches in combinational logic?

Three rules prevent latches: (1) assign default values at the beginning of combinational always @(*) blocks, (2) always include a default case in case statements, and (3) ensure every output is assigned in every possible path through the logic. The reference includes examples of each prevention technique.

How do I write a testbench in Verilog?

A testbench module has no ports. Declare reg signals for DUT inputs and wire signals for DUT outputs. Generate a clock with "always #5 clk = ~clk". Use initial blocks for reset sequences and stimulus. Include $dumpfile/$dumpvars for waveform output. The reference provides a complete testbench template with self-checking assertions.

What are CDC techniques for clock domain crossing?

For single-bit signals, use a 2-FF synchronizer: two flip-flops in the destination clock domain to reduce metastability probability. For multi-bit signals, use Gray code encoding or an asynchronous FIFO. For pulse transfer, use a toggle-based handshake synchronizer. The reference includes complete code examples for each technique.

What synthesis attributes does this reference include?

The reference covers Xilinx attributes (dont_touch, mark_debug, ram_style for BRAM/LUTRAM selection, fsm_encoding for one-hot/binary), Intel/Altera attributes (syn_encoding), and general synthesis pragmas (translate_off/on for simulation-only code, full_case/parallel_case for case optimization).