VLSI Design Reference

The reference covers minimum width rules per metal layer, minimum spacing rules including width-dependent spacing, enclosure rules for via-to-metal relationships, extension rules, metal density requirements for CMP uniformity (typically 20%-80% in a 50um window), and antenna rules that protect gate oxide during plasma etching. Each rule includes specific numerical examples from advanced nodes and EDA tool syntax in both Calibre SVRF and Synopsys IC Validator formats.

The DRC section covers the complete flow from layout data preparation through rule file loading, DRC execution, and violation review using Calibre and IC Validator. The LVS section explains netlist extraction, schematic comparison, and result interpretation (CORRECT vs INCORRECT with specific mismatch types). A dedicated LVS debugging entry covers common errors like shorts, opens, device mismatches, and net mismatches with cross-probing techniques.

The reference covers RC extraction with StarRC command syntax, extraction modes (RC, R, C, RCC), parasitic model formulas for resistance, ground capacitance, and coupling capacitance. It explains coupling capacitance effects including crosstalk noise, crosstalk delay, and the Miller effect (K factors 0, 1, 2). Full 3D extraction for FinFET structures is covered along with accuracy comparisons (2D: 15%, 2.5D: 5%, 3D: 2% error). SPEF file format is documented with annotated structure examples.

The reference provides detailed characteristics for 7nm (N7), 5nm (N5), and 3nm (N3) process nodes from TSMC and Samsung. This includes transistor type (FinFET vs GAA Nanosheet), fin/sheet pitch, metal pitch, gate length, supply voltage, gate density (transistors per mm2), and EUV adoption level. Design challenges at each node are discussed, including self-aligned patterning, increasing parasitic RC, and thermal power density management.

The STA section covers PrimeTime command syntax for reading netlists, liberty libraries, SDC constraints, and SPEF parasitics. It explains setup and hold time conditions with formulas and timing diagrams, clock skew concepts, and on-chip variation (OCV) derating methods including AOCV and POCV. The SDC entry provides complete constraint examples for clock definitions, generated clocks, I/O delays, false paths, multicycle paths, and transition/capacitance limits.

The reference covers all power components: dynamic power (P_switching = alpha * C * Vdd^2 * f), short-circuit power, and static leakage power. It includes PrimePower analysis commands, example power breakdowns (dynamic vs leakage percentages), and optimization techniques (clock gating, multi-Vt, power gating, DVFS). IR drop analysis covers both static and dynamic IR drop with RedHawk commands and typical limits (static < 5% Vdd, dynamic < 10% Vdd).

Yes. The reference is structured to be educational as well as practical. It starts with fundamental concepts like lambda-based design rules and MOSFET scaling laws, progresses through standard cell library structure and cell characterization, and covers advanced topics like 3D extraction and POCV timing analysis. The numerical examples and EDA tool commands make it useful for both coursework and professional chip design projects.

Yes. This is a purely client-side reference that loads entirely in your browser. No design data, search queries, or usage patterns are transmitted to any server. The tool is safe to use alongside proprietary PDK information or confidential project data. No EDA license, account registration, or software download is required.