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PLL Loop Calculator

Free web tool: PLL Loop Calculator

Output Frequency

1.000 GHz

PFD Frequency

10.000 MHz

Loop Bandwidth

100.000 kHz

Loop Filter Components (2nd order)

R1

40.00 Ω

C1

96.06 nF

C2

16.48 nF

About PLL Loop Calculator

The PLL Loop Filter Calculator helps RF and mixed-signal engineers design the passive loop filter for a Phase-Locked Loop (PLL) frequency synthesizer. By entering the reference frequency, frequency divider ratio N, charge pump current, VCO gain (Kvco in MHz/V), target loop bandwidth, and desired phase margin, the calculator computes the exact resistor and capacitor values needed for either a 2nd order or 3rd order passive loop filter.

Phase-locked loops are fundamental building blocks in RF transceivers, clock generation circuits, frequency synthesizers, and communication systems. The loop filter is the most critical passive component in the PLL — it sets the loop bandwidth, determines phase margin (stability), filters reference spurs, and controls lock time. Getting the filter component values right is essential for achieving low phase noise close to the carrier, adequate spur rejection, and fast frequency hopping.

Technically, the calculator uses classical PLL loop filter design theory. For a 2nd order filter (R1, C1, C2), it solves for the time constants T1 and T2 from the target phase margin using T1 = (sec(PM) + tan(PM)) / ωc and T2 = 1 / (ωc² × T1). The open-loop gain condition at the crossover frequency ωc = 2π × BW yields C1 = (Icp × Kvco × √((1+(ωcT1)²)/(1+(ωcT2)²))) / (N × ωc²). The 3rd order filter adds C3 = C1/10 and R3 = T3/C3 to suppress high-frequency spurs with an additional pole.

Key Features

  • Designs 2nd order passive PLL loop filter (R1, C1, C2) from system parameters
  • Designs 3rd order passive PLL loop filter (R1, C1, C2, R3, C3) with spur rejection pole
  • Calculates output frequency fout = fref × N and PFD frequency for verification
  • Target loop bandwidth input in kHz with exact ωc used in the design equations
  • Target phase margin input in degrees for loop stability control (typically 45°–60°)
  • Component values auto-formatted in pF/nF/µF and Ω/kΩ/MΩ for readability
  • Supports reference frequency input in kHz, MHz, or GHz units
  • Real-time recalculation whenever any PLL parameter changes

Frequently Asked Questions

What is a PLL loop filter and why is it needed?

A PLL loop filter is a low-pass filter placed between the charge pump output and the VCO control input. It integrates the charge pump current pulses into a smooth DC voltage that controls the VCO frequency, while suppressing reference frequency spurs and out-of-band noise. Without a loop filter, the VCO would oscillate erratically in response to every phase detector pulse.

What is loop bandwidth and how does it affect PLL performance?

Loop bandwidth (typically 1–10% of the reference frequency) is the frequency at which the open-loop gain crosses 0 dB. A wider bandwidth means faster lock time, better suppression of VCO noise, but poorer rejection of reference spurs. A narrower bandwidth locks more slowly, passes more VCO phase noise, but better attenuates reference frequency artifacts. The optimal bandwidth depends on which noise source (VCO or reference/charge-pump) dominates.

What is phase margin and what value should I target?

Phase margin is the amount of additional phase shift the loop can tolerate before becoming unstable (180° phase shift causes oscillation). Phase margin = 180° − |phase of open-loop transfer function at ωc|. Standard recommendations are 45°–60°. Less than 45° risks ringing and instability; more than 60° degrades lock time and spur performance. A target of 50°–55° is a common practical choice.

What is the difference between 2nd and 3rd order loop filters?

A 2nd order loop filter (R1, C1, C2) creates one zero (from R1-C1) and two poles (at DC from C1+C2, and a high-frequency pole from C2). It provides adequate phase margin and spur filtering for many applications. A 3rd order filter adds an extra RC section (R3, C3) that creates an additional pole to further suppress reference spurs, at the cost of slightly reduced phase margin (which the design equations compensate by placing C3 = C1/10 and T3 = T1/10).

What is charge pump current (Icp) and how does it affect the filter?

The charge pump current is the current sourced or sunk by the charge pump when the PFD detects a phase error. Higher Icp increases the open-loop gain, which in turn requires larger C1 to maintain the same loop bandwidth. Increasing Icp while reducing C values can help when physical component values become too large or too small for practical PCB implementation. Typical values range from 0.1 mA to 5 mA.

What is Kvco (VCO gain) and where do I find it?

Kvco is the voltage-controlled oscillator's tuning sensitivity, expressed in MHz/V. It describes how much the VCO output frequency changes per volt of control voltage change. This parameter is found in the VCO datasheet, typically specified at the center of the tuning range. Kvco varies with frequency and tuning voltage, so use the value at your operating point. Typical values range from a few MHz/V (low-noise VCOs) to several hundred MHz/V (wide-tuning VCOs).

What divider ratio N should I use?

N = fout / fref is the integer or fractional division ratio between the VCO output frequency and the reference frequency. For a 1 GHz VCO output with a 10 MHz reference, N = 100. In fractional-N synthesizers, N is a non-integer average controlled by a delta-sigma modulator, allowing finer frequency resolution without reducing fref. Enter the exact integer N or the average fractional N for your operating point.

How accurate are the calculated component values for a real PCB?

The calculated values are theoretical starting points based on ideal loop filter equations. In practice, you should simulate the PLL open-loop transfer function using the calculated values in a SPICE or specialized PLL tool (ADIsimPLL, HMC Synthesizer Tool, etc.) and then verify on a prototype. Real capacitor and resistor tolerances, PCB parasitics, and VCO Kvco variation across tuning range will cause the actual loop bandwidth and phase margin to differ from targets, usually by 10–20%.